U.S. Pat. No. 4,063,078 describes a clock generation network for generating at least a pair of non-overlapping clock trains from a single oscillator input. The network complies with so-called Level Sensitive Scan Design (LSSD) rules which are, in turn, described in U.S. Pat. Nos. 3,761,695; 3,783,254 and 3,784,907. A logic network designed within the LSSD rules requires sequential logic to be controlled by two or more non-overlapping clock trains. The purpose of LSSD is to enable logic networks embodied in large scale integrated semiconductor devices to be adequately tested. The clock generation network of the aforementioned. U.S. Pat. No. 4,063,078 has the advantage that it is fully testable, it can be integrated on the same semiconductor chip as logic circuits conforming to the LSSD rules, and during the test the test generation system can generate tests for the clock network as well as the logic network it controls.
It is often required to use the well-established "D" type edge trigger in high speed counting and other situations. Unfortunately, although a `D`-type edge trigger can be economically fabricated from six NAND gates, it contains several feedback paths which are very difficult to test by automatic test pattern generation without using additional input/output terminals. Additionally such a trigger would not conform to the LSSD rules mentioned above.